The integrated circuit chip packaging structure of the present invention provides high density integrated circuit packaging and excellent electrical performance (i.e. power distribution, impedance matching, minimal cross talk). In preferred form, this invention relates to using a semiconductor substrate as the base of a semiconductor packaging structure to which a plurality of integrated circuit chips are attached.
The concept of using a semiconductor substrate as a base substrate for a semiconductor packaging structure is known in the art. In particular, packages have been proposed using silicon as the base substrate, and having silicon chips mounted thereon. Major problems associated with these packages are that the power distribution systems are limited in their ability to appropriately provide power to the chips, and the inherent resistivity of the silicon make the substrate a poor media for transmitting signals.
The following references represent efforts made in this field of packaging.
Bergendahl et al., in an article published in the Proceedings of the IEEE Customs Integrated Circuits Conference, June 1985, titled "The Wafer Transmission Module--Wafer Integration Packaging" and in an article published in VLSI Systems Design, January 1986, titled "The Wafer Transmission Module", describe a silicon wafer substrate that contains interconnect wiring and power busses The Wafer Transmission Module uses silicon as a means for multi-chip wafer scale integration for the purpose of large scale integration. It allows many chips to share the same package without requiring 100 percent yield of the chips. Integrated circuit chips are diced, tested and mounted on the module and wire bonded to module interconnect wiring. The signal propagation time of the interconnections is minimized by the use of tall thin film lossy transmission lines which are known in the state of the art. Large line width and spacing improve the yield and reduce interline coupling but also limit wirability and density.
Similar techniques are also described by Johnson et al., in "The Significance of Wafer Scale Integration in Computer Design", in the IEEE Proceedings of International Conference Computer Design, October 1984. Johnson et al. do not provide packages with adequate connections to the outside world. Furthermore, the lack of isolation lines between adjoining signal lines requires substantial interline spacing, thus reducing overall wirability and density. The proposal lacks an efficient power distribution system, thus creating a highly resistive and inductive environment. Moreover, the absence of adequate control of the impedance limits the application of the teaching to low performance technology and makes it inadequate for bipolar circuitry, which requires controlled impedance and small voltage swings.
Technological advancements in the field of thin film technology have made the use of thin film metallurgy attractive in silicon based packaging structures.
Stopper et al. in U.S. Pat. No. 4,458,297 disclose an electrically programmable thin-film interconnection system. Layers of conductors, insulators and a special amorphous-silicon alloy are deposited and patterned on a silicon wafer with conventional processing techniques. The completed structure provides a large number of unconnected wiring elements that can be linked by electrically programmable fuses. Thus, any desired interconnection network can be derived from a standard process. The aforementioned technique has several limitations. The package lacks the flexibility and the compactness required by VLSI packages and lends itself to only low performance applications where the speed of electrical signals is not essential. Wirability is inherently limited. The use of antifuses creates serious stubbing problems due to signal reflections on all unterminated studs. Impedance is not finely controlled using the Stopper et al. package.
Spielberger et al., in an article entitled "Silicon on Silicon Packaging", published in the IEEE Transaction on Components, Hybrids and Manufacturing Technology, June 1984 describe a silicon-on-silicon package wherein silicon is used as a multi-chip substrate. A plurality of integrated circuit chips are flip bonded by controlled collapse joining to a silicon base substrate. The substrate provides the interconnections between chips and the next level of packaging. The substrate is then epoxy bonded to a ceramic substrate and the package is then completed by wire bonding and hermetically sealing. The proposed assembly uses interconnecting aluminum wires that are 50 microns wide and power busses that are 200 microns wide, thus having limited wiring density.
Otsuka et al., in UK Pat. No. GB 2,132,411 describe a silicon carbide substrate wherein high electrical insulation, high thermal conductivity and a coefficient of expansion similar to that of silicon is achieved. This concept is further expanded by Satoh, et al., in a paper presented at the International Conference on Computer Design of October 1984, "A High Speed Multi-Chip RAM Module with Thermal Stress Free Configuration", wherein face-down multiple LSI chips are bonded to a silicon substrate. The silicon substrate with LSI chips is bonded to a silicon carbide base. Silicon carbide has a dielectric constant of 40, thus degrading the electrical characteristics of the electrical signals because of the high capacitive nature of the silicon carbide.
Dielectrics such as polyimide are also utilized in silicon packaging applications. The ability to form fine lines, 5 microns wide, with thin film metal technology and fine spacings in multilayer additive substrates where polyimide is used as a dielectric demonstrates the potential of using thin film metal and polyimide.
Landis, of ITT Corporation, in an article titled: "High-Speed Packaging for GaAs Interconnection" published by the 35th Electronic Components Conference dated May 20, 1985 describes a multilayer, fine-line polyimide chip carrier containing nine 64-pin LSI chips. The fine-line, additive polyimide technology provides the capability of constructing a substrate whereby chip-to-chip interconnections have fully shielded coaxial conductors. Each semiconductor is assembled onto die attach copper studs and wire bonded to the substrate. The coaxial conductors have been designed to reduce the effects of cross-talk between adjacent high density signal lines. Whereas the package construction finds useful application for high speed operation, it is limited by the inherent complexity of the process. Furthermore, the significant number of metallization steps severely limits the final yield of the product, and the large amount of surrounding metal increases the capacitance of the signal lines thereby increasing the current demand and deteriorating the thermal characteristics of the package.
Chong et al. of Trilogy Systems Corporation in an article "A High Density Multichip Memory Module", published July 1, 1985 by Trilogy Systems Corporation describe an approach of using thin film interconnect technology to package a pluralrty of VLSI logic and memory chips on a single module as a means of achieving Wafer Scale Integration. The module is based on a thin film copper-polymer technology which displays advantages over multi-layer ceramic technology when comparing interconnect delays and interconnect densities. The module substrate is assembled in a conventional dual in line package upon which are mounted CMOS memory chips and chip capacitors for high frequency bypassing. The package lacks capability for high I/O density and is thus restricted to low performance applications. Thus, it would be inadequate for high speed, high I/O count, bipolar applications.
Magdo et al. in U.S. Pat. No. 4,023,197, disclose an integrated circuit chip carrier with multi-level metallurgy in which the effects of the metallurgy in causing irregularities at the various levels is minimized. Magdo et al. disclose a structure and a process to provide a carrier for advanced integrated circuit chips of high circuit densities which is structurally compatible with such chips. The package lacks a low inductance power distribution system and requires complex processing.
Thus, there is a need in the art for providing an improved semiconductor packaging structure having; a base substrate made of semiconductor material, alternating insulation and metallization layers, and semiconductor integrated circuit chips mounted thereon. An additional need exists for the semiconductor packaging structure to have efficient power distribution therein, and to provide high quality signal transmission (i.e. minimal cross-talk between signal lines, little or no dispersion, and matched impedances). Such signal transmission should be accomplished with minimum delay between successive signals, thus increasing the speed of signal transmission.
There is a further need in the art for the semiconductor packaging structure to provide high density wiring and have few wirability constraints.
The need also exists for the semiconductor packaging structure to have impedances that are matched so that resistance and capacitance between metallization levels is at a minimum.
A further need exists for there to be little or no thermal coefficient of expansion mismatches between the base semiconductor substrate and integrated circuit chips mounted thereon.
There is also a need for the semiconductor packaging structure to have a flexible wire rerouting system that can easily provide for engineering changes or repairs as required. The need also exists for the semiconductor packaging structure to have signal lines wherein the capacitance is low, thus decreasing current demands and decreasing the thermal output of the module.
There is a need in the art for a process of manufacturing the improved semiconductor packaging structure. A further need exists for a high yield process of manufacturing the semiconductor packaging structure. There is still a further need for the process to require a minimal number of metallization steps.